International Journal of Innovative Research in Engineering & Multidisciplinary Physical Sciences
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Synthesization of Low Power Digital Signal Processor Architecture

Authors: Krishnakishore Palla, Y Naveen Kumar, P Sreenivasulu, P Khesshawa Kumar

DOI: https://doi.org/10.17605/OSF.IO/65EGH

Short DOI: https://doi.org/ggkv74

Country: India

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Abstract: A Wireless Sensor Networks spatially distributed autonomous sensors to monitor physical or environmental conditions, such as temperature, sound, pressure, etc. Radio communication exhibits the highest energy consumption in wireless sensor nodes. This paper describes the design of the newly proposed folded-tree architecture for on-the-node data processing in wireless sensor networks, using parallel prefix operations and data locality in hardware.

Keywords: Wireless sensor nodes, Folded-tree, Parallel prefix operations.


Paper Id: 166

Published On: 2017-04-19

Published In: Volume 5, Issue 2, March-April 2017

Cite This: Synthesization of Low Power Digital Signal Processor Architecture - Krishnakishore Palla, Y Naveen Kumar, P Sreenivasulu, P Khesshawa Kumar - IJIRMPS Volume 5, Issue 2, March-April 2017. DOI 10.17605/OSF.IO/65EGH

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